China crafts 3nm transistors without EUV via stacked nanosheets
The race for the smallest, most powerful semiconductor chips is currently defined by access to cutting-edge tools. For nations seeking technological independence, the ability to develop advanced manufacturing processes without relying on foreign-controlled equipment is a strategic imperative. This pursuit has led to remarkable advancements, exemplified by the work of the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS).
IMECAS has recently unveiled an experimental process flow designed to build stacked-nanosheet gate-all-around (GAA) transistors using immersion DUV lithography. This breakthrough isn’t just an academic exercise; it represents a significant step toward China’s ambition to develop its own indigenous semiconductor evolution, especially in the realm of 3nm-class and smaller process technologies.
The significance of this work lies in demonstrating a viable route for developing future microchip architectures without requiring access to the most advanced tools, specifically EUV scanners, typically provided by Western companies. This achievement underscores the capability of Chinese researchers to push the boundaries of semiconductor physics and engineering independently.
In the process of integrating these advanced structures, the team achieved crucial early milestones. Researchers successfully fabricated stacked nanosheet-channel GAA transistors with DUV lithography, confirming that the gate control mechanism functioned effectively. They measured Ion/Ioff ratios of 9.7×10^5 and 7.6×10^5, both successfully surpassing the critical threshold of 5×10^5. This result proves that the gate can distinguish between conducting and non-conducting states in these novel structures.
However, while the functional validation is compelling, the team wisely focused on the foundational process flow rather than immediate commercial metrics. They intentionally held back detailed information regarding critical geometrical parameters—such as gate pitch, metal pitch, nanosheet dimensions, and transistor density—that would allow direct comparison to technologies produced by industry leaders like Intel, Samsung Foundry, or TSMC.
This careful approach frames the achievement not as a completed 3nm process, but as a robust validation of a DUV-based process flow for stacked-nanosheet GAA devices. The real innovation here is demonstrating a novel method for exploring these complex architectures outside the constraints of current leading-edge tools.
The underlying theory supporting this work is rooted in the successful transition from FinFET devices to GAA architectures, where surrounding the channel with nanosheets provides superior electrostatic control as device dimensions shrink. IMECAS has been investigating these critical transition technologies since 2020, focusing specifically on nodes below 3nm, making this DUV methodology a powerful tool for future innovation.
Ultimately, transforming this research into high-volume commercial manufacturing requires integrating numerous complex steps—from lithography and deposition to etching, cleaning, and precise material control. While IMECAS has successfully demonstrated the theoretical and experimental flow for researching these advanced transistors, the next, larger challenge remains the full integration required for production-ready 3nm-class technology.
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