SK hynix injects CPU cores into SSDs for faster speeds
SK hynix Unveils the Tiny, Efficient Core That Could Revolutionize SSDs
The relentless pursuit of faster data storage, driven by the insatiable demand of AI servers, is pushing the limits of traditional silicon architecture. As solid-state drives (SSDs) race toward higher IOPS and faster PCIe speeds, the CPUs managing these operations are struggling with scaling. SK hynix is tackling this challenge not by simply adding more cores, but by introducing a revolutionary architectural shift: the Hynix Transaction Processing Unit (H-TPU), a specialized core designed to handle the repetitive, power-intensive work of SSD controllers with unmatched efficiency.
The core issue lies in the sheer complexity of storage control. Managing the intricate details of read/write commands, metadata, and buffer control requires over a hundred functions—a task that overwhelms general-purpose CPU cores. As drive speeds and PCIe bandwidths continuously increase, controller CPUs reach a critical bottleneck regarding power consumption and physical area. This reality makes the “more cores” solutions favored by competitors, while logical, increasingly unsustainable for the demands of next-generation storage.
SK hynix’s answer is a paradigm shift. Instead of relying on bulky, general-purpose cores, the company has engineered the H-TPU—a set of tiny, programmable cores clustered together to manage these specific tasks. These units operate on a specialized four-stage, in-order pipeline, perfectly tailored for I/O operations. Crucially, these small clusters operate with incredible thrift: they are claimed to draw only about 2.5% of the power consumed by a general-purpose CPU core, utilizing only about 4% of its physical area.
This design philosophy is rooted in specialization. Rather than cramming all storage functions onto one monolithic CPU, SK hynix has broken down the workload into dozens of small TPU clusters, each dedicated to a specific job. This segmented approach allows the system to efficiently handle data flow, manage metadata, and control buffers with high precision, complemented by the main CPU which handles higher-level functions like error recovery and policy management.
The innovation extends beyond simple partitioning. Underlying patents detail a sophisticated split between a control plane (handled by the CPU) and an I/O plane (handled by the specialized processors). This architecture ensures that data ingestion and flow are processed efficiently through a dedicated pipeline, allowing the CPU to focus on managing exceptions and complex decisions, while the TPUs execute the raw data transfer.
Looking ahead, this specialized approach is designed for future evolution. The next phase involves Hardware Automation (HWA), where command processing and buffer copying can be moved into dedicated hardware circuits, further enhancing predictability and reducing latency. This evolution positions the H-TPU as a foundation for next-generation storage, preparing the way for future high-bandwidth flash (HBF) stacks that will be critical for AI inference.
By moving complex I/O tasks into highly efficient, specialized hardware, SK hynix is demonstrating a clear path forward. This specialized architecture addresses the fundamental scaling problem in storage, ensuring that as data demands escalate, the efficiency and speed of the hardware will keep pace. The H-TPU is not just a small core; it is a strategic evolution for the entire landscape of high-performance data infrastructure.
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