Tag: CPU Cores

  • AMD confirms low-power CPU cores in Linux kernel patch — Zen 6 chips could follow in Intel’s footsteps with new core type for background tasks

    Featured image AMD confirms lowpower CPU cores in Linux kernel patch  Zen 6 chips could follow in Intels footsteps with new core type for background t

    AMD Unlocks the Power of Three: How Heterogeneous Cores are Reshaping the Future of CPU Design

    In the relentless pursuit of efficiency and performance, processor architecture is constantly evolving. AMD has recently taken a significant step in this race, rolling out Linux kernel patches that introduce crucial support for its emerging low-power CPU cores. This move isn’t just a technical footnote; it signals a fundamental shift in how modern computing balances speed with energy conservation.

    The new update provides operating systems with the necessary intelligence to distinguish between different types of processing units within a single chip: high-performance cores, efficiency cores, and the newly introduced low-power cores. This clear categorization is essential for optimizing system behavior, allowing applications to utilize the right kind of core for the right task.

    At the heart of this innovation lies AMD’s approach to heterogeneous processors. By cleanly separating these core types, AMD makes it straightforward for software and the underlying hardware to manage power consumption effectively. The low-power cores are specifically engineered for tasks that don’t demand peak performance—perfect for background processes and idle operations where reducing energy use is the primary goal.

    As AMD engineer Vishal Badole explained, these specialized cores are designed to minimize energy expenditure during standby and background activities. This focus on efficiency allows the system to operate gracefully, ensuring that power consumption doesn’t become a limiting factor in daily computing.

    This strategy mirrors the broader industry trend currently being explored by competitors like Intel. Both companies are pushing toward architectures that blend high-speed processing with energy-efficient execution, aiming to deliver powerful performance without draining battery life or overheating systems.

    While AMD utilizes two distinct core types, their underlying architectural philosophy remains consistent: offering a dense core offering optimized for space. This approach contrasts with other designs that rely on entirely different microarchitectures, highlighting AMD’s commitment to an integrated and streamlined system design.

    Despite the successful implementation of these new distinctions, AMD has been relatively reserved in revealing the deep architectural details of the low-power cores. They have emphasized their purpose—optimizing for minimal power consumption during idle time—but have kept the specific differences from today’s dense Zen5c cores under wraps.

    Furthermore, no new scheduling policies or optimization logic were introduced by these kernel patches; the work is focused on identification and management. AMD has maintained its preference for using a consistent microarchitecture across CPU platforms, even while fine-tuning optimizations based on die size and clock speeds, a choice that simplifies software development.

    Ultimately, AMD‘s latest moves underscore a commitment to pushing the boundaries of processor design—proving that future computing will be defined not just by raw speed, but by intelligent, energy-aware efficiency.

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  • AMD’s next-gen Zen 6 CPU cores will come in a low-power compact flavour, which should help laptop batteries last even longer

    Featured image AMDs nextgen Zen 6 CPU cores will come in a lowpower compact flavour which should help laptop batteries last even longer

    Three years ago, AMD embarked on a journey to redefine how CPU cores are built by introducing a new architecture for its Zen 4 microarchitecture. The goal? To dramatically reduce the amount of silicon real estate taken up by a single core, paving the way for highly efficient chiplets.

    This compact design philosophy is now central to the Zen family. While this method has been a staple, Team Red is clearly preparing for the next evolution, signaling that another step toward efficiency is on the horizon with Zen 6.

    To formalize this architectural approach, AMD recently rolled out an update to the Linux kernel, detailing how it classifies CPU types. This extension brings the x86 topology classification to support a new category: the Low Power core type, in addition to Performance and Efficiency.

    Understanding these classifications is key to grasping modern CPU design philosophy. In AMD’s framework, performance cores are simply the traditional Zen blocks—the largest, boasting the highest boost clocks. The Efficiency types, like the compact Zen 4c and Zen 5c, are smaller in size, often possessing less L3 cache, and operate with lower boost frequencies.

    AMD‘s approach to defining core roles differs interestingly from Intel’s system. While both companies utilize Performance and Efficiency cores, their internal architectures diverge significantly. This distinction makes thread scheduling—ensuring background tasks land on the right type of core while demanding tasks get maximum resources—a complex balancing act for both AMD and Intel.

    AMD has defined a specific role for its future Low Power (LP) cores. These are designed to consume minimal power during idle or background workloads, identified via specialized CPUID instructions. This mirrors concepts seen in Intel’s LPE cores, which are also tuned to run with strict power limits, though their boost speeds are slightly attenuated.

    The physical implementation offers a telling contrast: AMD’s Zen cores share a unified architecture and instruction set across all types, whereas Intel’s P-cores and E-cores operate on distinct internal systems. This difference creates unique scheduling challenges for operating systems and chip designers alike.

    Looking ahead to Zen 6, AMD is focusing the introduction of these new LP cores primarily on mobile and low-power platforms, such as Ryzen APUs. This targets scenarios where extending battery life and minimizing power consumption are paramount, making future AMD-powered laptops particularly attractive.

    This focus on efficiency is already paying dividends in compact designs. For instance, models like the Ryzen AI 7 350 leverage a mix of Zen 5 and Zen 5c cores, while gaming setups utilizing components like Steam Machine feature Zen 4 and Zen 4c cores—a combination that successfully reduces die size and power consumption.

    Despite this direction, there remains a performance consideration. If AMD maintains an eight-unit CCX core complex in mobile Zen 6 processors, swapping some Efficiency cores for the new Low Power ones could lead to performance regression if those LP cores operate at lower boost clocks. However, there is considerable speculation that AMD may move toward a larger configuration, possibly a twelve-unit CCX design for Zen 6, which could offer an exceptional blend of power efficiency and raw performance across their mobile offerings.

  • Intel Raptor Lake Next Gaming Laptops Could Pack Up To 24 CPU Cores

    The world of high-performance computing is currently buzzing with speculation, particularly around Intel’s next major processor architecture. Whispers suggest that as developers race to keep pace with the demands of artificial intelligence and the soaring costs of memory, Intel might be making some unconventional architectural choices.

    There is persistent chatter regarding a forthcoming launch of what many are calling Raptor Lake Next. However, rather than focusing solely on bleeding-edge innovation, some analysts suggest this next generation may lean into a slightly older, yet highly pragmatic, architecture.

    This hypothetical pivot isn’t about slowing down progress; it’s presented as a strategic response to the massive constraints currently facing the industry. The primary bottleneck? The severe shortage and skyrocketing prices of DDR5 memory, which is becoming a critical choke point for everyone building powerful systems.

    The current environment, fueled by the insatiable appetite of AI development, has placed immense pressure on supply chains. As demand for specialized components surges, manufacturers are navigating a landscape where cost and availability often dictate design decisions more than pure theoretical performance benchmarks.

    This is where the speculation solidifies into intriguing theory: Intel’s approach to Raptor Lake Next could be viewed as a necessary salve. By potentially leveraging a slightly older, more readily available architecture, the company might be sidestepping some of the immediate supply chain headaches associated with cutting-edge component procurement.

    Notable industry observers, including those who monitor deep leaks, have pointed toward this possibility. For instance, X user Jaykihn (@jaykihn0), a recognized source of technical insight, has shared perspectives suggesting that Intel’s roadmap may prioritize stability and supply management in this crucial period.

    It highlights a fascinating tension in the technology world: the desire for the absolute latest innovation versus the harsh realities of global economics and material scarcity. Whether this architectural decision proves to be a smart strategic retreat or a temporary measure remains to be seen, but it certainly adds an interesting layer of complexity to the ongoing race for computing dominance.