HardwareFreaks

Tag: Process Nodes

  • Intel expands production of photomasks in California: EUV and High-NA EUV in the focal point

    Featured image Intel expands production of photomasks in California EUV and HighNA EUV in the focal point

    Intel is powering up its future of chipmaking by significantly expanding its mask production capabilities, cementing Santa Clara’s status as a powerhouse in semiconductor manufacturing. The company recently initiated construction on a major expansion of its Bowers Campus, designed to dramatically increase the production of photomasks—the crucial templates required for etching and manufacturing advanced microchips within the United States.

    This strategic move is more than just adding square footage; it represents a deep commitment to reinforcing Intel’s position as a key producer of these essential reticles. The new facility will house advanced manufacturing equipment, ensuring that the company can meet the intense demand for high-precision masks necessary for next-generation technologies.

    The expanded operations are geared toward handling highly demanding processes, specifically enabling the creation of 6-inch by 6-inch photomasks for both DUV and EUV layers. This capacity extends across a wide spectrum of semiconductor nodes, ranging from mature designs down to extremely advanced 1.4nm-class technologies.

    The primary focus of this expansion is supporting Intel’s leading-edge process technologies, including the development of the 18A-P and 14A nodes, as well as the critical steps toward the decade-defining 10A and 7A processes. These advanced manufacturing methods require increasingly intricate photomasks featuring extremely dense patterns and sophisticated curvilinear optical proximity correction.

    Having a world-class mask writing shop is non-negotiable in the semiconductor industry, where every revision directly impacts production schedules. Producing these masks in-house offers a crucial advantage, especially when dealing with EUV layers, where tools can damage masks over time. By bringing mask production in-house, Intel ensures rapid turnaround and superior quality for these sensitive components.

    Adding to this internal strength is Intel’s unique ability to manage the entire process chain. The company is the only semiconductor producer to operate its own tools for photomask writing through its IMS Nanofabrication subsidiary. This unique infrastructure utilizes multi-beam mask writers (MBMWs), which project hundreds of independently programmable electron beams simultaneously, achieving massive throughput with nanometer-scale accuracy.

    The Bowers Campus in Santa Clara has served as the core infrastructure for Intel’s mask production since 1986. Now, by expanding this site, Intel is not only boosting its internal capacity but is actively reinforcing the commitment to advancing U.S. semiconductor manufacturing leadership and supporting the global ecosystem of cutting-edge chip fabrication.

    Intel

    Credit: Tom’s Hardware

  • I can barely afford AMD and Nvidia’s current 4 nm chips, so I’m not sure what to make of IBM’s new sub-1 nm technology

    Featured image I can barely afford AMD and Nvidias current 4 nm chips so Im not sure what to make of IBMs new sub1 nm technology

    The high-performance world of graphics processing units (GPUs) is built on a foundation of cutting-edge silicon, but the race to the nanoscale is only just beginning. Today’s story isn’t just about faster games or more powerful AI; it’s about whether the physical limits of matter are about to be redefined by a new chip architecture.

    At the heart of this technological push is the intense competition among silicon giants. Companies like AMD and Nvidia currently rely on chips built on 4 nm-class silicon supplied by TSMC. As fabrication pushes into denser and smaller realms, so too does the pressure to innovate—and inevitably, to raise prices for chip designers.

    Meanwhile, a seismic shift is being whispered from the world of pure research: IBM has announced the introduction of what they claim to be the world’s first sub-1 nanometer (nm) chip technology. This breakthrough centers around an innovative transistor architecture operating at the 0.7 nm, or 7 angstrom node.

    IBM’s vision is wrapped up in a concept they call nanostack”>nanostack, which represents the industry’s first known three-dimensional, nanosheet-based design. This revolutionary architecture vertically stacks and staggers transistors, utilizing 3D sequential integration to pack an astonishing nearly 100 billion transistors onto a chip the size of a fingernail.

    This vertical stacking is designed to unlock new performance efficiencies by allowing different material combinations within each stacked layer, optimizing both power consumption and operational speed for every transistor independently.

    Of course, navigating the landscape of silicon nodes can be tricky. It is notoriously difficult to compare specifications across competing manufacturers like TSMC, Intel, and IBM, as marketing terms often overshadow the technical reality. Terms like TSMC’s N3 or Intel’s 18A are more frequently used as branding than precise physical measurements.

    Despite the evolving nomenclature, a closer look at the actual transistor density suggests an interesting parallel between the players. While some might assume that newer node names imply superior performance, analytical comparisons indicate that the transistor density achieved by TSMC’s N3 node is already on par with, or potentially even better than, Intel‘s 18A technology.

    This subtle comparison highlights a critical economic conundrum facing the industry. While IBM promises incredible physical density and theoretical performance gains, the real sticking point remains cost. The fundamental question now shifts from “how small can we make the transistors?” to “how much will it actually cost to manufacture them?”

    If groundbreaking advancements in silicon technology do not come with a corresponding reduction in manufacturing expense, the ultimate measure of progress hinges on economic viability. The next great hurdle for chip makers will be determining whether these incredible feats of nanoscale engineering can keep Moore’s Law alive and ensure that future technological leaps are accessible to everyone.

    Credit: PC Gamer