Three years ago, AMD embarked on a journey to redefine how CPU cores are built by introducing a new architecture for its Zen 4 microarchitecture. The goal? To dramatically reduce the amount of silicon real estate taken up by a single core, paving the way for highly efficient chiplets.
This compact design philosophy is now central to the Zen family. While this method has been a staple, Team Red is clearly preparing for the next evolution, signaling that another step toward efficiency is on the horizon with Zen 6.
To formalize this architectural approach, AMD recently rolled out an update to the Linux kernel, detailing how it classifies CPU types. This extension brings the x86 topology classification to support a new category: the Low Power core type, in addition to Performance and Efficiency.
Understanding these classifications is key to grasping modern CPU design philosophy. In AMD’s framework, performance cores are simply the traditional Zen blocks—the largest, boasting the highest boost clocks. The Efficiency types, like the compact Zen 4c and Zen 5c, are smaller in size, often possessing less L3 cache, and operate with lower boost frequencies.
AMD‘s approach to defining core roles differs interestingly from Intel’s system. While both companies utilize Performance and Efficiency cores, their internal architectures diverge significantly. This distinction makes thread scheduling—ensuring background tasks land on the right type of core while demanding tasks get maximum resources—a complex balancing act for both AMD and Intel.
AMD has defined a specific role for its future Low Power (LP) cores. These are designed to consume minimal power during idle or background workloads, identified via specialized CPUID instructions. This mirrors concepts seen in Intel’s LPE cores, which are also tuned to run with strict power limits, though their boost speeds are slightly attenuated.
The physical implementation offers a telling contrast: AMD’s Zen cores share a unified architecture and instruction set across all types, whereas Intel’s P-cores and E-cores operate on distinct internal systems. This difference creates unique scheduling challenges for operating systems and chip designers alike.
Looking ahead to Zen 6, AMD is focusing the introduction of these new LP cores primarily on mobile and low-power platforms, such as Ryzen APUs. This targets scenarios where extending battery life and minimizing power consumption are paramount, making future AMD-powered laptops particularly attractive.
This focus on efficiency is already paying dividends in compact designs. For instance, models like the Ryzen AI 7 350 leverage a mix of Zen 5 and Zen 5c cores, while gaming setups utilizing components like Steam Machine feature Zen 4 and Zen 4c cores—a combination that successfully reduces die size and power consumption.
Despite this direction, there remains a performance consideration. If AMD maintains an eight-unit CCX core complex in mobile Zen 6 processors, swapping some Efficiency cores for the new Low Power ones could lead to performance regression if those LP cores operate at lower boost clocks. However, there is considerable speculation that AMD may move toward a larger configuration, possibly a twelve-unit CCX design for Zen 6, which could offer an exceptional blend of power efficiency and raw performance across their mobile offerings.
Credit: PC Gamer
