HardwareFreaks

Tag: AI Accelerator

  • Nvidia reportedly cancels quad-die Rubin Ultra GPU in favor of dual-GPU design, report claims — complex design purportedly scrapped over ‘manufacturing execution concerns’

    Featured image Nvidia reportedly cancels quaddie Rubin Ultra GPU in favor of dualGPU design report claims complex design purportedly scrapped over ma

    When designing the next generation of artificial intelligence accelerators, ambition often outpaces engineering reality. Nvidia’s pursuit of an unbeatable performance solution for its Rubin Ultra AI accelerator involved a blueprint that pushed the boundaries of semiconductor packaging, only to encounter significant roadblocks in the manufacturing execution phase.

    The original vision called for utilizing four GPU chiplets to power the Rubin Ultra, promising a substantial leap in performance compared to previous generations. This design was not just about doubling speed; it sought to introduce unprecedented complexity into data center GPUs by connecting these four near reticle-sized dies using advanced packaging technologies.

    However, realizing this ambitious layout proved to be a monumental engineering challenge. The difficulty lay not only in managing the connections between four complex dies but also in handling the immense cooling demands for those chips and the sixteen High-Bandwidth Memory (HBM4E) modules required. These manufacturing execution concerns made the four-chiplet approach prohibitively hard and costly to produce at scale.

    Consequently, Nvidia made a strategic pivot, choosing a path that prioritized manufacturability over maximum theoretical density. The company reportedly canceled the four-compute-chiplet design in favor of a more practical dual-GPU configuration.

    This shift in architecture naturally impacted the final product. The resulting Rubin Ultra accelerator will be approximately half as powerful as the original proposed design, though Nvidia plans to continue optimizing the new structure to squeeze out additional performance from the AI engine.

    The decision also brought changes to memory specifications. Rather than utilizing sixteen HBM4E modules, the updated design will use eight, which has broader implications for the overall HBM market.

    Furthermore, Nvidia is pushing forward with advanced memory technology; the Rubin Ultra will incorporate HBM4E memory, moving beyond the HBM4 used in earlier Rubin models. Looking ahead, Nvidia is also focused on scaling this performance through liquid-cooled Kyber rack-scale systems, aiming to pack at least 144 packages into a single scale-up domain.

    While the cancellation of the original design shifts some immediate metrics, the overall picture for partners remains complex. Since Nvidia focuses heavily on delivering rack-scale solutions rather than just individual GPUs, the impact on customer spending will depend on how this pivot influences the purchasing strategy for system-level compute versus standalone accelerators.

    Credit: Tom’s Hardware

  • Broadcom and OpenAI unveil custom-built Jalapeño inference processor — OpenAI’s first chip is a massive reticle-sized ASIC built in an ultra-fast nine-month development cycle

    The race for AI supremacy isn’t just about bigger models; it’s about smarter hardware. This is where OpenAI and Broadcom are throwing down a serious challenge with Jalapeño, a custom-built inference processor designed from the ground up to power the next generation of large language models and agentic AI workloads.

    Jalapeño is not just another AI accelerator. It is presented as a purpose-built inference ASIC, meticulously engineered around the specific behaviors of LLMs. Rather than repurposing existing training hardware, the architecture addresses fundamental bottlenecks that plague large-scale AI: inefficient data movement, the crucial balance between compute and memory resources, networking efficiency, and overall operational behavior.

    At the heart of Jalapeño’s design is a focus on maximizing both throughput and minimizing latency. To achieve this, the team opted for a sophisticated configuration, utilizing a massive compute chiplet surrounded by six high-bandwidth HBM memory modules. This design choice allows the processor to execute demanding reasoning and agentic tasks with exceptional efficiency.

    The promise of Jalapeño lies in its efficiency. The companies claim that this optimized architecture delivers performance per watt substantially higher than current state-of-the-art hardware, suggesting a dramatic leap in energy efficiency for complex AI calculations. While specific benchmarks remain under wraps, internal testing indicates that the chip is efficiently executing cutting-edge workloads, including GPT-5.3-Codex-Spark.

    The physical reality of Jalapeño underscores its ambition. Engineering samples are already operating successfully in the lab, and the development cycle itself was remarkably swift, reaching tape-out in just nine months. This acceleration was made possible by integrating artificial intelligence into the chip design process, alongside Broadcom’s established practice of reusing logic across multiple custom designs.

    The design philosophy extends beyond immediate use. Jalapeño is envisioned to support not only OpenAI’s initiatives but also the broader industry of LLMs, potentially positioning it as a platform that others can leverage. The goal is to create a scalable physical infrastructure capable of handling the demands of the next decade of AI.

    Broadcom‘s CEO emphasized this vision, stating that the collaboration with OpenAI represents a fundamental commitment to scaling the physical infrastructure needed for future AI deployment. This hardware is slated for deployment in gigawatt-scale data centers starting in 2026, working alongside partners like Microsoft.

    The implications are vast. By prioritizing these holistic architectural considerations—from kernel execution to memory architecture—Jalapeño aims to set a new benchmark for how AI compute is delivered, pushing the boundaries of what modern silicon can achieve.

    Credit: Tom’s Hardware