China’s 7nm chip leap bypasses EUV limits

The high-stakes world of semiconductor manufacturing is currently defined by an intense technological sprint, where foundry capabilities and chip design methodologies are pushing the boundaries of what silicon can achieve. At the heart of this battle lies a fascinating analysis of process nodes, transistor density, and the complex ways technology translates into real-world performance.

Recent deep dives into the architecture behind systems like Huawei’s Kirin 9030 have brought into sharp focus the capabilities of China’s semiconductor infrastructure. An examination of SMIC’s third-generation 7nm-class fabrication technology, known as N+3, reveals impressive engineering feats. This process utilizes a minimum metal pitch that is nominally tighter than the approximately 36nm pitch found in many high-performance cells within Intel’s Panther Lake CPU architecture.

While density is a powerful metric for measuring manufacturing prowess, it doesn’t tell the whole story of chip competitiveness. Despite achieving this compact layout, simply packing more transistors into a smaller space does not automatically equate to superior performance or energy efficiency. The real benchmark for modern computing lies in how effectively those transistors are utilized.

The numbers speak for themselves regarding density: SMIC’s N+3 process reportedly achieves a transistor density of around 113.4 million transistors per square millimeter. This figure is even higher than that achieved by TSMC’s N6, which manages 107.7 million transistors per square millimeter. This achievement signals a significant capability in manufacturing processes that rely on advanced techniques like DUV multi-patterning and extensive design-technology co-optimization.

How did SMIC reach this level of density? The success wasn’t accidental; it required highly complex methods. Analysts suggest that SMIC employed sophisticated techniques, including reduced fin counts, placing contacts directly over active gates, and tightening cell isolation. These strategies boost transistor density but introduce increased complexity, cost risks, and design constraints into the manufacturing pipeline.

When comparing this progress to competitors like Intel’s 18A or TSMC’s N2 and N3 nodes, the conclusion is nuanced. While SMIC achieves a tight metal pitch, competitors like Intel 18A offer advantages in overall transistor density coupled with superior performance efficiency. Furthermore, architectures like 18A utilize advanced features such as gate-all-around transistors and backside power delivery, which are highly advantageous for both mobile SoCs and data center applications.

The journey of semiconductor scaling is clearly ongoing. Even amidst current export restrictions that have influenced China’s technological pace, innovation continues unabated. Experts believe that by continuing to focus on tighter metal layers, smaller standard cells, and eventual backside power delivery, SMIC has the potential to push density even further.

Looking ahead, if this scaling momentum continues, future nodes like N+4 could approach the density of TSMC N5, and N+5 incorporating backside power delivery might reach levels comparable to Intel 18A. Ultimately, while manufacturing density is an impressive feat, the true measure of success in the chipmaking race remains optimizing performance and power efficiency.