Google could build more AI chips than Nvidia by 2028

The race for the ultimate AI hardware is heating up, not just in the realm of software, but in the silicon itself. At the forefront of this colossal engineering effort is Google, which is moving beyond simply consuming AI power to designing its own custom accelerators that could redefine the entire market. Google’s ambition is staggering: they are reportedly planning to order between 12 and 15 million of their proprietary Tensor Processing Units (TPUs) by 2028.

This isn’t just a procurement exercise; it signals a massive commitment to vertical integration. By aiming for the V9 generation of TPUs in 2028, Google is betting big on its custom architecture, which reportedly utilizes four compute dies—a sophisticated strategy that speaks to a major engineering feat. If these projections hold true, Google may not only match or surpass Nvidia’s supply of AI accelerators but could ultimately become the world’s largest owner of highly capable AI hardware.

The implications for the rest of the industry are profound. If Google successfully achieves this volume, it positions itself to dominate the AI hardware landscape. This shift underscores a vital trend: hyperscalers are increasingly designing chips tailored exactly to their unique software stacks and data center demands, rather than relying solely on off-the-shelf solutions.

However, building these custom processors presents formidable manufacturing hurdles. While Google targets massive output, the reality of semiconductor production involves navigating complex supply chains. Experts suggest that relying solely on current capacity from foundries like TSMC may not be enough to meet this demand by 2028. This necessity pushes major players toward vertically integrated solutions.

This brings us to the critical role of Intel Foundry Services. Reports indicate that Google is exploring Intel’s capacity, suggesting a potential reliance on Intel to bridge the gap in production volume. This move introduces a fascinating technical challenge: chiplet design requires advanced packaging technologies, and current methods used by rivals like TSMC and Intel are not directly compatible.

The incompatibility between competing packaging standards—such as Intel’s EMIB/EMIB-T and TSMC’s CoWoS-L—means that achieving Google’s vision requires innovative solutions. This situation emphasizes that the battle isn’t just about raw processing power, but about mastering the intricate dance of hardware design, manufacturing, and packaging.

Ultimately, while volume might shift in favor of a custom chip fleet, Nvidia’s position remains entrenched. The dominant factor will likely be the software ecosystem; the competitive edge of AI accelerators continues to hinge on powerful software stacks, such as Nvidia‘s CUDA, rather than sheer silicon quantity. For rivals, the challenge lies not just in capacity, but in matching that foundational software advantage.