Hybrid AI ASIC: Google and AMD Integrate On-Package CPUs

The Next Frontier: How Google and AMD Are Redefining AI Hardware

The race for the next generation of artificial intelligence hardware is moving beyond sheer accelerator power, venturing into a fascinating new territory where general-purpose computing meets specialized AI acceleration. At the forefront of this shift is a potential collaboration between tech giants Google and AMD, hinting at a fundamental redesign of how we build intelligent systems.

Sources suggest that this partnership could involve integrating AMD’s CPU cores into Google’s forthcoming 10th-generation Tensor Processing Units (TPUs). This isn’t just a simple hardware swap; it signals a serious exploration into creating an entirely new type of AI chip—one that combines proprietary accelerator technology with on-board general-purpose processing capabilities.

Why this focus on the CPU? While large language model (LLM) training remains overwhelmingly accelerator-heavy, the cutting edge of AI research, particularly in reinforcement learning and agentic models, is increasingly demanding more general-purpose compute around specialized operations. These workloads require sophisticated reasoning that benefits immensely from powerful CPU cores.

Google is already subtly acknowledging this need within its current architecture. For example, their latest inference-oriented TPU systems, designed for tasks like reasoning and reinforcement learning, feature dedicated Axion CPUs. Yet, the trend suggests an even closer integration: some analyses point toward optimizing the ratio of CPUs to accelerators, suggesting that the future of AI might be significantly more CPU-heavy than previously imagined.

This is where AMD’s expertise becomes critical. By involving a CPU maker in a custom AI ASIC project for Google, AMD would mark its first major step into designing highly customized AI silicon. This move leverages AMD’s deep knowledge of advanced packaging and System-on-Chip (SoIC) technology—skills essential for creating integrated data center solutions.

The real promise lies in unifying the compute. Bringing CPU cores directly into the TPU package offers a tantalizing opportunity to reduce the distance between general-purpose processing and tensor calculations. This architectural consolidation promises significant gains in performance and power efficiency, streamlining how AI operations are executed.

AMD is uniquely positioned for this integration, having already developed data center-grade designs, such as the Instinct MI300A, that successfully pack both x86 processors and accelerator chiplets together. This experience positions them perfectly to help Google engineer a tightly integrated package where TPU compute chiplets are seamlessly linked with AMD CPU and high-bandwidth memory.

Whether this collaboration results in fully custom accelerators or simply an innovative approach to blending existing silicon, the ultimate outcome is clear: the next wave of AI hardware will be defined not just by raw speed, but by intelligent integration. It marks a pivotal moment where general computing power becomes inseparable from specialized AI acceleration.