IBM’s dual-ISA core natively executes ARM and z/Architecture
IBM Unifies Mainframes with Dual-ISA Core, Redefining Enterprise Computing
The future of enterprise computing is being built on a foundation of unparalleled reliability and massive scale. At the heart of this revolution is IBM’s latest processor, which shatters traditional boundaries by introducing the first processor to natively support dual instruction set architecture (ISA) execution within a single core. This groundbreaking innovation, born from a deep collaboration between IBM and Arm, promises to unify deployment and unlock vast new opportunities for businesses operating on mission-critical systems.
Instead of relying on separate x86 servers, Arm infrastructure, and z/Architecture mainframes for different tasks, IBM has engineered a chip that treats both ISAs as “first-class citizens.” This processor can execute either z/Architecture or AArch64 instructions dynamically, switching between them in mere nanoseconds. This approach eliminates fragmentation, allowing organizations to leverage the entire Arm software ecosystem directly on the robust mainframe platform.
This design philosophy centers on maximizing reliability. IBM insists that the dual-ISA core retains the legacy strength of mainframes while embracing modern software demands. To ensure this stability, the system relies on Linux Kernel-level Virtual Machine (KVM) to support AArch64 instructions, mirroring the established method used to support Linux on Z mainframes. This careful integration ensures that the phenomenal uptime, which IBM claims as 99.999999%, remains uncompromising, equating to just 0.032 seconds of downtime per year.
The engineering deep dive reveals a powerhouse chip featuring 11 high-performance cores built on a cutting-edge 2nm process, capable of operating at a base frequency of 5.7 GHz. Beyond the cores, the chip boasts expansive caches, including 432 MB of virtual L3 and 3.5 GB of virtual L4, providing substantial memory bandwidth and speed for complex data flow.
Crucially, the innovation extends beyond the core itself. IBM has also introduced a next-generation AI accelerator, the Spyre, which is significantly more capable than previous models. This new accelerator features 16 cores optimized for newer AI data formats, including FP4/MXFP4, enabling faster and more efficient processing of complex machine learning workloads.
The leap in performance is further amplified by a radical shift in memory technology. Moving away from LPDDR5, IBM is adopting lower-capacity but vastly higher-bandwidth HBM3e. Each accelerator is equipped with 96 GB of HBM3e memory, delivering up to 4TB/s of throughput—a 20-fold increase over what was previously possible with LPDDR5. This memory upgrade ensures that the massive computational power of the dual-ISA core is not bottlenecked by data transfer.
The architectural work focused heavily on the core itself, implementing a full hardware support for AArch64 v9.3 with Scalable Vector Extension (SVE). By streamlining instruction decoding and utilizing intelligent cache tagging, IBM has achieved a cohesive design. This move demonstrates a clear vision: to deliver the scale and stability of mainframe computing while providing the flexibility required by the rapidly evolving demands of modern AI and software development.
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