Pulling apart a chip validates PCIe 6.0 in a 3D stack
Bridging the Gap: How Silicon Is Mastering the 3D Revolution in PCIe
The future of high-speed data transmission is rapidly moving into three dimensions, and silicon designers are leading the charge. Synopsys has recently published compelling silicon results for what is considered the first 3D PCIe 6.0 test chip, demonstrating a significant leap in how complex high-speed interfaces can be engineered.
This breakthrough centers on a sophisticated 5nm Physical Layer (PHY) built directly into a face-to-face stacked package. This architecture manages to achieve blistering performance: operating at 64 GT/s per lane and supporting up to 128 GB/s across an eight-lane link using the advanced PAM4 signaling technique. Crucially, the system successfully cleared the stringent bit error rate requirements set by the PCIe 6.0 standard, proving that high density and high speed are not mutually exclusive.
Achieving this feat required more than just stacking components; it demanded a fundamental rethinking of chip design. The Synopsys team achieved this by taking an existing 2D PCIe 6.0 test chip and radically transforming it. They incorporated through-silicon vias (TSVs) and completely redesigned the circuit layout against 3D process design kits. This process highlights the massive engineering effort required to transition from conventional planar layouts to true three-dimensional integration.
The challenges in 3D design are complex. In traditional monolithic chips, high-speed signals are kept short and manageable by placing the PHYs near the package I/O. However, in stacked designs, the signals must travel through vias, demanding careful routing and buffering. As Synopsys noted, this architectural shift introduces new variables regarding electromigration and layout rules, making the design process an iterative dance between bandwidth demands and signal integrity.
The use of PAM4 signaling further enhances this efficiency. By packing two bits into each signal symbol, PAM4 significantly reduces the error margin compared to older NRZ signaling used in PCIe 5.0, offering a denser and more robust means of data transmission. This efficiency is key to squeezing maximum performance from the dense 3D structure.
Other industry leaders are pursuing parallel paths toward this stacked reality. For instance, in advanced processors like Fujitsu’s Monaka, the approach involves stacking compute chiplets face-to-face using hybrid copper bonding. Rather than integrating PHYs inside the stack, memory controllers and I/O die are placed separately, demonstrating that diverse solutions exist for achieving high-performance integration.
Looking ahead, the industry is poised for the next evolution: 3.5D packaging. This paradigm shift involves relocating critical components, such as PCIe PHYs, to an interposer—a multi-protocol hub that handles connectivity for Ethernet, PCIe, and CXL. While a definitive timeline is still being determined, leading-edge customers are already evaluating angstrom-class process technologies for the top dies in their stacks, signaling that the next frontier of silicon integration is already in sight.
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