HardwareFreaks

Tag: Chiplets

  • Nvidia reportedly cancels quad-die Rubin Ultra GPU in favor of dual-GPU design, report claims — complex design purportedly scrapped over ‘manufacturing execution concerns’

    Featured image Nvidia reportedly cancels quaddie Rubin Ultra GPU in favor of dualGPU design report claims complex design purportedly scrapped over ma

    When designing the next generation of artificial intelligence accelerators, ambition often outpaces engineering reality. Nvidia’s pursuit of an unbeatable performance solution for its Rubin Ultra AI accelerator involved a blueprint that pushed the boundaries of semiconductor packaging, only to encounter significant roadblocks in the manufacturing execution phase.

    The original vision called for utilizing four GPU chiplets to power the Rubin Ultra, promising a substantial leap in performance compared to previous generations. This design was not just about doubling speed; it sought to introduce unprecedented complexity into data center GPUs by connecting these four near reticle-sized dies using advanced packaging technologies.

    However, realizing this ambitious layout proved to be a monumental engineering challenge. The difficulty lay not only in managing the connections between four complex dies but also in handling the immense cooling demands for those chips and the sixteen High-Bandwidth Memory (HBM4E) modules required. These manufacturing execution concerns made the four-chiplet approach prohibitively hard and costly to produce at scale.

    Consequently, Nvidia made a strategic pivot, choosing a path that prioritized manufacturability over maximum theoretical density. The company reportedly canceled the four-compute-chiplet design in favor of a more practical dual-GPU configuration.

    This shift in architecture naturally impacted the final product. The resulting Rubin Ultra accelerator will be approximately half as powerful as the original proposed design, though Nvidia plans to continue optimizing the new structure to squeeze out additional performance from the AI engine.

    The decision also brought changes to memory specifications. Rather than utilizing sixteen HBM4E modules, the updated design will use eight, which has broader implications for the overall HBM market.

    Furthermore, Nvidia is pushing forward with advanced memory technology; the Rubin Ultra will incorporate HBM4E memory, moving beyond the HBM4 used in earlier Rubin models. Looking ahead, Nvidia is also focused on scaling this performance through liquid-cooled Kyber rack-scale systems, aiming to pack at least 144 packages into a single scale-up domain.

    While the cancellation of the original design shifts some immediate metrics, the overall picture for partners remains complex. Since Nvidia focuses heavily on delivering rack-scale solutions rather than just individual GPUs, the impact on customer spending will depend on how this pivot influences the purchasing strategy for system-level compute versus standalone accelerators.

    Credit: Tom’s Hardware

  • AMD’s next-gen Zen 6 CPU cores will come in a low-power compact flavour, which should help laptop batteries last even longer

    Featured image AMDs nextgen Zen 6 CPU cores will come in a lowpower compact flavour which should help laptop batteries last even longer

    Three years ago, AMD embarked on a journey to redefine how CPU cores are built by introducing a new architecture for its Zen 4 microarchitecture. The goal? To dramatically reduce the amount of silicon real estate taken up by a single core, paving the way for highly efficient chiplets.

    This compact design philosophy is now central to the Zen family. While this method has been a staple, Team Red is clearly preparing for the next evolution, signaling that another step toward efficiency is on the horizon with Zen 6.

    To formalize this architectural approach, AMD recently rolled out an update to the Linux kernel, detailing how it classifies CPU types. This extension brings the x86 topology classification to support a new category: the Low Power core type, in addition to Performance and Efficiency.

    Understanding these classifications is key to grasping modern CPU design philosophy. In AMD’s framework, performance cores are simply the traditional Zen blocks—the largest, boasting the highest boost clocks. The Efficiency types, like the compact Zen 4c and Zen 5c, are smaller in size, often possessing less L3 cache, and operate with lower boost frequencies.

    AMD‘s approach to defining core roles differs interestingly from Intel’s system. While both companies utilize Performance and Efficiency cores, their internal architectures diverge significantly. This distinction makes thread scheduling—ensuring background tasks land on the right type of core while demanding tasks get maximum resources—a complex balancing act for both AMD and Intel.

    AMD has defined a specific role for its future Low Power (LP) cores. These are designed to consume minimal power during idle or background workloads, identified via specialized CPUID instructions. This mirrors concepts seen in Intel’s LPE cores, which are also tuned to run with strict power limits, though their boost speeds are slightly attenuated.

    The physical implementation offers a telling contrast: AMD’s Zen cores share a unified architecture and instruction set across all types, whereas Intel’s P-cores and E-cores operate on distinct internal systems. This difference creates unique scheduling challenges for operating systems and chip designers alike.

    Looking ahead to Zen 6, AMD is focusing the introduction of these new LP cores primarily on mobile and low-power platforms, such as Ryzen APUs. This targets scenarios where extending battery life and minimizing power consumption are paramount, making future AMD-powered laptops particularly attractive.

    This focus on efficiency is already paying dividends in compact designs. For instance, models like the Ryzen AI 7 350 leverage a mix of Zen 5 and Zen 5c cores, while gaming setups utilizing components like Steam Machine feature Zen 4 and Zen 4c cores—a combination that successfully reduces die size and power consumption.

    Despite this direction, there remains a performance consideration. If AMD maintains an eight-unit CCX core complex in mobile Zen 6 processors, swapping some Efficiency cores for the new Low Power ones could lead to performance regression if those LP cores operate at lower boost clocks. However, there is considerable speculation that AMD may move toward a larger configuration, possibly a twelve-unit CCX design for Zen 6, which could offer an exceptional blend of power efficiency and raw performance across their mobile offerings.

    Credit: PC Gamer