HardwareFreaks

Tag: Energy Efficiency

  • AMD Zen 6 Takes A Page From Intel With New Low-Power Cores

    The race for processor supremacy is heating up, and behind the scenes, innovation is flowing faster than ever. While headlines often focus on marketing hype, the real revolution in computing often happens deep within the silicon architecture, where engineers are subtly reshaping the very foundation of performance.

    In this latest architectural evolution, AMD is making a significant move that promises to redefine efficiency and power management for its upcoming CPUs. The news isn’t just about incremental updates; it’s about fundamentally changing how these powerful processors interact with the operating system.

    AMD’s Vishal Badole recently submitted a critical patch for the Linux Kernel, introducing support for an entirely new class of processing units. This update officially integrates support for a Low Power core type into the established architecture, alongside the existing Performance and Efficiency types.

    This addition is far more than a simple label; it represents a sophisticated design choice aimed directly at addressing the growing demands of modern computing. By introducing specialized low-power cores, AMD is giving system designers the flexibility to dynamically allocate resources, ensuring that tasks are handled with maximum energy efficiency without sacrificing peak performance when needed.

    For system builders and developers, this means a new level of granularity in power management. It allows operating systems to intelligently manage workloads, shifting operations to the most efficient cores while keeping critical processes running smoothly. This level of fine-tuning is essential for optimizing battery life in portable devices and maximizing performance in demanding applications.

    The integration of these specialized cores signals a commitment to delivering not just raw speed, but intelligent, sustainable computing. As the industry continues its rapid progression toward more power-conscious hardware, AMD’s approach underscores a dedication to creating processors that are both exhilaratingly fast and remarkably efficient.

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    Credit: HotHardware

  • AMD confirms low-power CPU cores in Linux kernel patch — Zen 6 chips could follow in Intel’s footsteps with new core type for background tasks

    Featured image AMD confirms lowpower CPU cores in Linux kernel patch Zen 6 chips could follow in Intels footsteps with new core type for background t

    AMD Unlocks the Power of Three: How Heterogeneous Cores are Reshaping the Future of CPU Design

    In the relentless pursuit of efficiency and performance, processor architecture is constantly evolving. AMD has recently taken a significant step in this race, rolling out Linux kernel patches that introduce crucial support for its emerging low-power CPU cores. This move isn’t just a technical footnote; it signals a fundamental shift in how modern computing balances speed with energy conservation.

    The new update provides operating systems with the necessary intelligence to distinguish between different types of processing units within a single chip: high-performance cores, efficiency cores, and the newly introduced low-power cores. This clear categorization is essential for optimizing system behavior, allowing applications to utilize the right kind of core for the right task.

    At the heart of this innovation lies AMD’s approach to heterogeneous processors. By cleanly separating these core types, AMD makes it straightforward for software and the underlying hardware to manage power consumption effectively. The low-power cores are specifically engineered for tasks that don’t demand peak performance—perfect for background processes and idle operations where reducing energy use is the primary goal.

    As AMD engineer Vishal Badole explained, these specialized cores are designed to minimize energy expenditure during standby and background activities. This focus on efficiency allows the system to operate gracefully, ensuring that power consumption doesn’t become a limiting factor in daily computing.

    This strategy mirrors the broader industry trend currently being explored by competitors like Intel. Both companies are pushing toward architectures that blend high-speed processing with energy-efficient execution, aiming to deliver powerful performance without draining battery life or overheating systems.

    While AMD utilizes two distinct core types, their underlying architectural philosophy remains consistent: offering a dense core offering optimized for space. This approach contrasts with other designs that rely on entirely different microarchitectures, highlighting AMD’s commitment to an integrated and streamlined system design.

    Despite the successful implementation of these new distinctions, AMD has been relatively reserved in revealing the deep architectural details of the low-power cores. They have emphasized their purpose—optimizing for minimal power consumption during idle time—but have kept the specific differences from today’s dense Zen5c cores under wraps.

    Furthermore, no new scheduling policies or optimization logic were introduced by these kernel patches; the work is focused on identification and management. AMD has maintained its preference for using a consistent microarchitecture across CPU platforms, even while fine-tuning optimizations based on die size and clock speeds, a choice that simplifies software development.

    Ultimately, AMD‘s latest moves underscore a commitment to pushing the boundaries of processor design—proving that future computing will be defined not just by raw speed, but by intelligent, energy-aware efficiency.

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    Credit: Tom’s Hardware

  • IBM goes sub-1nm, develops 0.7nm-class technology — offering up to 50% higher performance and 70% higher energy efficiency compared to IBM’s 2nm-class node

    IBM Unveils Next-Generation Chip Architecture Using Stacked Transistors

    In a move poised to redefine the limits of semiconductor physics, IBM has announced the production of the first test chip utilizing its 0.7nm-class fabrication technology. This breakthrough is anchored by a revolutionary concept: the use of nanostack transistors, marking the industry’s first sub-1nm manufacturing process.

    The secret to this leap lies in reimagining how transistors are built. Instead of relying on conventional planar geometry, IBM employs a novel arrangement that utilizes two wafers instead of one for active transistor tiers, bonded together with ultra-thin dielectric material. This innovative nanostack architecture fundamentally alters the way logic transistors are organized, promising dramatic gains in power, performance, and area (PPA) compared to previous generations.

    The payoff is substantial. IBM claims that this new approach delivers up to 50% higher performance and a remarkable 70% boost in energy efficiency when compared to their existing 2nm-class node. Furthermore, the nanosheet architecture offers an astonishing 40% increase in SRAM density and further improvements for logic transistors—gains that are exceptionally difficult to achieve in current manufacturing techniques.

    How does this vertical stacking work? In traditional semiconductor design, complementary n-type and p-type transistors sit side by side. IBM’s nanostack concept separates these types into vertically bonded tiers, essentially transforming the transistor layout from a two-dimensional arrangement into a more efficient three-dimensional stack. This separation allows for independent optimization of the n-type and p-type channels using different materials and geometries.

    This technique offers significant physical advantages, effectively halving the lateral footprint required for CMOS pairs and resulting in roughly double the transistor density compared to monolithic designs. It conceptualizes a solution that resembles CFETs while employing an entirely distinct bonding method.

    However, pushing the boundaries of silicon is rarely without complexity. Implementing this dual-wafer approach introduces several engineering hurdles that must be navigated. Achieving perfect alignment and bonding yield between two advanced logic wafers is critical, as any defect at the interface can compromise the entire stack. Routing power delivery also becomes more intricate with multiple active device tiers, and managing thermal dissipation becomes challenging when one layer is physically separated from the heat sink.

    Furthermore, the manufacturing process itself comes with a cost penalty. Producing two advanced FEOL wafers, along with the additional bonding and thinning steps, increases complexity. The feasibility of this method hinges on whether the resulting density, SRAM, and performance gains sufficiently offset these manufacturing difficulties and increased costs.

    While IBM suggests that this technology is perfectly suited for specialized, heavy-duty applications, such as data center AI solutions—which thrive on massive density—it acknowledges that it may not be the immediate path for mainstream client processors. Nevertheless, IBM remains optimistic, suggesting that these advancements could lead to mass production within the next five years by leveraging pre-competitive intellectual property and know-how.

    Credit: Tom’s Hardware

  • Nvidia announces liquid cooling system that runs ‘hotter than a hot tub’ — promises to reduce electricity consumption and cut water use by up to 100%, but sustainability challenges remain

    The race for sustainable technology is heating up, and it seems that at the heart of powering the next generation of artificial intelligence lies a surprisingly refreshing solution: liquid cooling fueled by smart thermodynamics.

    Nvidia, the titan of AI GPU manufacturing, has just unveiled a radical new approach to data center cooling, introducing a system they describe as hotter than a hot tub. This isn’t just about getting the chips to run cool; it’s about redefining how massive computing centers manage heat, promising significant reductions in both water and electricity consumption.

    The innovation sits at the intersection of physics and efficiency. By circulating coolant—a blend of 75% water and 25% propylene glycol—at a high temperature of 113 degrees F (45 degrees C), Nvidia is setting a new benchmark for thermal management in AI factories. While this might sound counterintuitive, the system handles the intense heat generated by Rubin chips effectively, exiting the loop at 131 degrees F (55 degrees C).

    The real breakthrough lies in the efficiency gains derived from operating at higher base temperatures. Traditional water-cooling systems often consume nearly 40% of a data center’s total power, and these setups frequently lose water through evaporation. This new closed-loop system flips the script by minimizing water waste entirely; Nvidia claims it allows for up to a 100% reduction in water consumption, enabling facilities to “fill once and run closed for the life of the facility.”

    This high operating temperature offers a powerful pathway toward greater energy savings. Since 113 degrees F is often higher than ambient air temperatures, data centers can utilize outdoor dry coolers to dissipate heat directly into the environment, dramatically reducing the need for conventional chillers. This approach allows facilities to run their cooling plants far more efficiently.

    Expert analysis suggests that optimizing chiller targets can yield substantial savings. Adjusting a chiller plant’s target temperature by just 1.8 degrees F (1 degree C) can reduce electricity costs by 4%. By allowing systems to operate closer to the 113 degrees F benchmark, data centers can reduce the workload on chillers, leading to significant power consumption cuts.

    While this solution tackles the cooling aspect brilliantly, it addresses a broader set of concerns facing the AI industry. Traditional air-cooled facilities generate noise pollution, and the reliance on fossil fuel power plants for energy generation remains an environmental challenge that demands continuous attention.

    Despite these hurdles, this shift is undeniably a step in the right direction toward making artificial intelligence more sustainable. As the technology rolls out, it will take time for widespread adoption to occur, but the foundation for cooler, greener data centers is firmly being laid.

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    Credit: Tom’s Hardware