HardwareFreaks

Tag: Moore’s Law

  • I can barely afford AMD and Nvidia’s current 4 nm chips, so I’m not sure what to make of IBM’s new sub-1 nm technology

    Featured image I can barely afford AMD and Nvidias current 4 nm chips so Im not sure what to make of IBMs new sub1 nm technology

    The high-performance world of graphics processing units (GPUs) is built on a foundation of cutting-edge silicon, but the race to the nanoscale is only just beginning. Today’s story isn’t just about faster games or more powerful AI; it’s about whether the physical limits of matter are about to be redefined by a new chip architecture.

    At the heart of this technological push is the intense competition among silicon giants. Companies like AMD and Nvidia currently rely on chips built on 4 nm-class silicon supplied by TSMC. As fabrication pushes into denser and smaller realms, so too does the pressure to innovate—and inevitably, to raise prices for chip designers.

    Meanwhile, a seismic shift is being whispered from the world of pure research: IBM has announced the introduction of what they claim to be the world’s first sub-1 nanometer (nm) chip technology. This breakthrough centers around an innovative transistor architecture operating at the 0.7 nm, or 7 angstrom node.

    IBM’s vision is wrapped up in a concept they call nanostack”>nanostack, which represents the industry’s first known three-dimensional, nanosheet-based design. This revolutionary architecture vertically stacks and staggers transistors, utilizing 3D sequential integration to pack an astonishing nearly 100 billion transistors onto a chip the size of a fingernail.

    This vertical stacking is designed to unlock new performance efficiencies by allowing different material combinations within each stacked layer, optimizing both power consumption and operational speed for every transistor independently.

    Of course, navigating the landscape of silicon nodes can be tricky. It is notoriously difficult to compare specifications across competing manufacturers like TSMC, Intel, and IBM, as marketing terms often overshadow the technical reality. Terms like TSMC’s N3 or Intel’s 18A are more frequently used as branding than precise physical measurements.

    Despite the evolving nomenclature, a closer look at the actual transistor density suggests an interesting parallel between the players. While some might assume that newer node names imply superior performance, analytical comparisons indicate that the transistor density achieved by TSMC’s N3 node is already on par with, or potentially even better than, Intel‘s 18A technology.

    This subtle comparison highlights a critical economic conundrum facing the industry. While IBM promises incredible physical density and theoretical performance gains, the real sticking point remains cost. The fundamental question now shifts from “how small can we make the transistors?” to “how much will it actually cost to manufacture them?”

    If groundbreaking advancements in silicon technology do not come with a corresponding reduction in manufacturing expense, the ultimate measure of progress hinges on economic viability. The next great hurdle for chip makers will be determining whether these incredible feats of nanoscale engineering can keep Moore’s Law alive and ensure that future technological leaps are accessible to everyone.

    Credit: PC Gamer

  • Imec’s 2026 roadmap details 0.3nm nodes by 2038, CFET transistors become viable at 0.7nm — company redefines Moore’s Law as cell sizes gain importance for density

    Redefining Reality: How the Semiconductor Roadmap is Rewriting Moore’s Law

    The journey to smaller, faster chips is less about shrinking transistors and more about reinventing the way we build them. At the heart of this revolution is Imec’s ambitious semiconductor process technology roadmap, which doesn’t just predict timelines—it outlines the radical shifts required to continue the industry’s incredible march forward over the next few decades.

    This comprehensive view details the challenges ahead while showcasing the groundbreaking cooperation between leaders like TSMC, Intel, Nvidia, AMD, Samsung, and ASML. It provides a blueprint for achieving what feels increasingly impossible in modern chip design.

    While the general direction points toward 3 angstrom-class (0.3nm) fabrication technologies by 2038, the path isn’t a straight line. Imec’s research reveals important scaling limits; for instance, contact poly pitch (CPP) is projected to stall at A10 in 2030. This realization signals that continuing traditional Moore’s Law scaling will require more than just smaller gates—it demands entirely new architectural approaches.

    To keep the pace up, chipmakers must embrace novel technologies. The roadmap points toward adopting advanced solutions like Hyper-NA EUV Lithography systems and developing novel transistor concepts, such as CFET transistors, which allow for stacking devices vertically to achieve density gains.

    The Evolution of Transistor Architecture

    As fabrication complexity grows, the industry is moving away from launching entirely new process technologies every couple of years. Instead, a more measured approach is taking hold, with chipmakers rolling out incremental enhancements and node generations periodically. For example, TSMC has demonstrated this cadence by ramping up N3B, then N3E, and N3P in quick succession.

    Current generation nodes, such as the 2nm-class era (N2), already present interesting scaling puzzles. While some leaders are pushing performance gains through physical dimensions, others are finding ways to optimize density within existing constraints. This is where the future of density will be found: not just in shrinking individual transistors, but in vertical integration.

    Imec’s vision for the next few decades heavily emphasizes this 3D approach. As we look toward the A7 generation in 2033, conventional nanosheet architectures face scaling challenges. This is precisely why CFETs—transistors that stack n-type and p-type devices vertically—are positioned as a leading contender for production insertion. This shift represents a fundamental change: density gains will stem from fitting more logic gates into the same area through diverse architectural strategies rather than simply shrinking gate pitch.

    Redefining Moore’s Law

    The most exciting takeaway from the roadmap is that it forces us to redefine what Moore’s Law truly means. If contact poly pitch remains relatively stable across future nodes, density gains must come from smarter design and integration. This leads to a focus on the size of standard cells—the fundamental building blocks of logic—rather than the physical dimensions of individual transistors.

    By focusing on minimizing the footprint of these standardized logic cell areas, designers can extract massive density improvements. The transition from 6-track cells at N2 to potentially 3-track cells at A3 illustrates this principle: as we move forward, shrinking the standard-cell height will become just as critical as reducing transistor pitch.

    Furthermore, the future is defined by Heterogeneous Large-Scale Integration (HLSI). This concept shifts focus from optimizing individual components to creating unified compute platforms that seamlessly combine logic, memory, power delivery, and optical I/O through advanced 3D and 2.5D packaging.

    To manage this complexity, Imec has established the Cross-Technology Co-Optimization (XTCO) framework. XTCO assesses how diverse technologies—from logic development to cooling solutions—interact on system metrics like energy efficiency, thermal performance, and compute density. This holistic view acknowledges that future success depends not just on silicon shrinking, but on mastering the entire ecosystem.

    Ultimately, achieving true scaling will depend on an integrated approach: maximizing transistor density through vertical integration, optimizing power delivery via backside solutions, and mastering thermal management to handle the exponential increase in compute density. The next era of semiconductor technology is less about shrinking gates and more about building smarter, cooler systems.

    Credit: Tom’s Hardware

  • IBM Just Shattered Moore’s Law With Sub-1 Nanometer Chips

    The landscape of computing is undergoing a seismic shift. A massive leap in microchip design has just been announced by IBM, introducing a revolutionary new approach that promises to redefine the physical limits of what silicon technology can achieve.

    IBM has unveiled what it terms the world’s first sub-1 nanometer chip technology. This breakthrough isn’t just an incremental update; it represents a fundamental redesign of how transistors are built, establishing a completely new architectural paradigm known as nanostack”>nanostack.

    At the heart of this innovation is a staggering achievement in manufacturing precision. The new process allows for the creation of chips using a highly advanced 0.7nm (seven angstrom) semiconductor process, successfully pushing technology significantly below the traditional 1-nanometer threshold.

    This reduction in scale is critical because it tackles one of the most persistent challenges in modern electronics: the relentless demand for greater processing power while simultaneously fighting against the physical limitations imposed by miniaturization. By moving past the 1-nm barrier, IBM has opened up an entirely new frontier for engineers and designers.

    The introduction of nanostack”>nanostack technology is more than just a smaller chip; it represents an entirely new transistor architecture. This structural change allows for unprecedented density and efficiency, enabling the creation of processors that can operate with vastly increased speed and power consumption.

    What this breakthrough means for the future is immense. As devices continue to shrink and demand more computational muscle—from advanced AI systems to next-generation mobile devices—the ability to reliably pack more functionality into a smaller space becomes paramount. IBM’s work tackles this challenge head-on, promising chips that are not only faster but also fundamentally more efficient.

    This technological advance signals a new era for semiconductor manufacturing. It suggests that the physical constraints of silicon might soon be pushed further, fueling an ongoing race to build incredibly dense and powerful computing systems. The nanostack”>nanostack approach isn’t just about shrinking lines; it’s about rethinking the very blueprint of digital computation.

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    Credit: HotHardware